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71M6543F/71M6543G Data Sheet
2.5.4.4 RTC Temperature Compensation
The 71M6543 can be configured to regularly measure die temperature, including in SLP and LCD modes
and while the MPU is halted. If enabled by OSC_COMP , this temperature information is automatically
used to correct for the temperature variation of the crystal. A table lookup method is used.
Table 43 shows I/O RAM registers involved in automatic RTC temperature compensation.
Table 43: I/O RAM Registers for RTC Temperature Compensation
Name
OSC_COMP
STEMP[10:3]
STEMP[2:0]
LKPADDR[6:0]
LKPAUTOI
LKPDAT[7:0]
LKP_RD
LKP_WR
Location
28A0[5]
2881[7:0]
2882[7:5]
2887[6:0]
2887[7]
2888[7:0]
2889[1]
2889[0]
Rst
0
–
0
0
0
0
0
Wk
0
–
0
0
0
0
0
Dir
R/W
R
R/W
R/W
R/W
R/W
R/W
Description
Enables the automatic update of RTC_P[16:0] and
RTC_Q[1:0] every time the temperature is measured.
The result of the temperature measurement (10-bits
of magnitude data plus a sign bit).
The address for reading and writing the RTC lookup
RAM.
Auto-increment flag. When set, LKPADDR[6:0] auto
increments every time LKP_RD or LKP_WR is pulsed.
The incremented address can be read at
LKPADDR[6:0] .
The data for reading and writing the RTC lookup
RAM.
Strobe bits for the RTC lookup RAM read and write.
When set, the LKPADDR[6:0] and LKPDAT registers
are used in a read or write operation. When a strobe is
set, it stays set until the operation completes, at which
time the strobe is cleared and LKPADDR[6:0] is
incremented if LKPAUTOI is set.
Referring to Figure 13 the table lookup method uses the 10-bits plus sign-bit value in STEMP[10:0]
right-shifted by two bits to obtain an 8-bit plus sign value (i.e., NV RAM Address = STEMP[10:0] /4). A
limiter ensures that the resulting look-up address is in the 6-bit plus sign range of -64 to +63 (decimal).
The 8-bit NV RAM content pointed to by the address is added as a 2’s complement value to 0x40000,
the nominal value of 4* RTC_P[16:0] + RTC_Q[1:0] .
Refer to 2.5.4.3 RTC Rate Control for information on the rate adjustments performed by registers
RTC_P[16:0] and RTC_Q[1:0] . The 8-bit values loaded in to NV RAM must be scaled correctly to produce
rate adjustments that are consistent with the equations given in 2.5.4.3 RTC Rate Control for RTC_P[16:0]
and RTC_Q[1:0]. Note that the sum of the looked-up 8-bit 2’s complement value and 0x40000 form a 19-
bit value, which is equal to 4* RTC_P[16:0] + RTC_Q[1:0], as shown in Figure 13. The output of the
Temperature Compensation is automatically loaded into the RTC_P[16:0] and RTC_Q[1:0] locations after
each look-up and summation operation.
STEM P
10+S
>>2
8+S
LIMIT
-256
-64
63
-64
63
255
6+S
Look Up
RAM
ADDR
Q
7+S
Σ
19
4*RTC_P+RTC_Q
19
0x40000
Figure 13: Automatic Temperature Compensation
The 128 NV RAM locations are organized in 2’s complement format. As mentioned above, the
STEMP[10:0] digital temperature values are scaled such that the corresponding NV RAM addresses are
equal to STEMP[10:0] /4 (limited in the range of -64 to +63). See 2.5.5 71M6543 Temperature Sensor on
page 53 for the equations to calculate temperature in degrees °C from the STEMP[10:0] reading.
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